The invention generally relates to computer bus systems and in particular to a system for transferring data between devices on different sides of a bus bridge.
To support the high-bandwidth data transfers demanded by modern computer applications, data is transmitted across buses at very high rates. To achieve reliable, high speed data transfer, a computer system often includes a number of buses arranged in a hierarchy and interconnected by devices known as bus bridges.
In essence, a bus bridge is a load isolating device that allows multiple devices to appear as a single capacitive load to the bus which they are bridged. Although the reduced capacitive loading increases the maximum frequency at which a bus can operate, the bridge adds a layer of complexity in the design and operation of the computer system. Further complexity can result if the bridge is used to interconnect different types of buses because the bridge will translate data, commands and other control signals between the two bus formats.
One reason that bus bridges add complexity is that requests to transfer data from a requester side of a bridge to a target side of the bridge must often be buffered in the bridge in order to support split transactions. Split transactions allow a device to submit a request (e.g., read or write) to a bus bridge over a first bus. Rather than maintaining the connection with the bus bridge while the bridge performs the requested transaction, the device disconnects from the bridge to allow other devices to have access to the bus bridge. After the bridge completes the requested transaction, the requesting device reconnects to the bridge and receives the transaction confirmation (e.g., the requested data).
One example of a split transaction is a Delayed Transaction as defined in the Peripheral Component Interconnect (PCI) Local Bus Specification, Rev. 2.1, Jun. 1, 1995, available from the PCI Special Interest Group, Portland, Oreg. After submitting a transaction request (e.g., a read request) to a bus bridge, the PCI device is required to disconnect from the bridge. The PCI device continually retries the transaction until the bus bridge provides the requested data.
It will be appreciated that any transaction that crosses the bus bridge will incur a latency penalty. Moreover, because the latency penalty is incurred with each transfer across the bridge, latency can be reduced by fetching larger blocks of data. However, inbound read latency as seen by the requesting PCI device increases with the size of the block of data fetched from memory because the bridge may need to arbitrate for and access the memory system several times before receiving all the requested data on behalf of the PCI device.
In addition, after providing the fetched data to the requesting device, the device is typically disconnected from the bridge to allow other devices to access the bridge. For applications where there are multiple PCI masters sharing and arbitrating for ownership of a single PCI bus, this technique works well because each PCI master is disconnected from the bridge after receiving the fetched data.
Many newer I/O devices (e.g., a Gigabit Ethernet card) typically transfer much larger blocks of data and require higher bandwidth. For such high bandwidth devices, it is not unusual for a single PCI device to control or own a PCI bus for extended periods of time. In fact, only one PCI device may be connected to the PCI bus. In such cases, however, fetching a single block and then disconnecting the PCI master after each read results in a very inefficient use of the PCI bus bandwidth.
Therefore, a need exists for a computer system that improves usage of I/O bus bandwidth, reduces inbound read latency, and permits either multiple masters or a single master to be serviced efficiently.